The invention relates generally to power semiconductor switching devices and, more particularly, to a method for forming silicon carbide vertical MOSFET devices having improved channel length uniformity for decreased channel resistance.
Silicon carbide (SiC) is a wide band gap material having a maximum breakdown electric field larger than that of silicon by about one order of magnitude. Thus, SiC has been considered as an advantageous material for use in the manufacture of next generation power semiconductor devices. Such devices include, for example, Schottky diodes, thyristors and vertical MOSFETs (metal oxide semiconductor field effect transistors).
Most power MOSFETs have a different structure than commonly known “lateral” MOSFETs, in that their electrical flow path is vertical and not planar. With a lateral structure, the current and breakdown voltage ratings of the MOSFET are both a function of the channel dimensions (respectively, the width and length of the channel), resulting in inefficient use of the device real estate. With a vertical structure, the voltage rating of the transistor is a function of the doping and thickness of the epitaxial layer, while the current rating is a function of the channel width and length. This makes it possible for the transistor to sustain both high blocking voltage and high current within a compact piece of semiconductor material.
In a conventionally formed vertical MOSFET (also referred to as a DMOSFET, or generally DMOS), selective area P-well regions are formed within a surface layer of a lightly doped N− drift layer (in an N-type device). In turn, selective area N+ source regions and more heavily doped P+ regions (for ohmic contact to the P-well) are formed within each P-well region to facilitate the vertical flow of drift current. A device channel length is thereby defined by the distance between the outer edges of the N+ source region and the outer edges of the P-well containing the N+ source region.
Because such regions within the drift layer are conventionally formed by dopant implantation using lithographically patterned masks, there is the potential for inconsistent channel lengths, as well as damage to the channel region due to the implantation steps themselves. These can, in turn, result in increased channel resistance. Moreover, the formation of multiple doped regions results in the use of several lithography mask levels, which increases device manufacturing costs and decreases throughput.
Accordingly, it would be desirable to be able to manufacture a SiC power switching device (e.g., DMOSFET) that provides a more uniform aligned channel with decreased resistance.